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1 ? fn8251.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x40430, x40431, x40434, x40435 4kbit eeprom triple voltage monitor with integrated cpu supervisor features ? monitoring voltages: 5v to 9v ? independent core voltage monitor ? triple voltage detection and reset assertion ?standard reset threshold settings. see selec- tion table on page 2. ?adjust low voltage reset threshold voltages using special programming sequence ?reset signal valid to v cc = 1v ?monitor three separate voltages ? fault detection register ? selectable power-on reset timeout (0.05s, 0.2s, 0.4s, 0.8s) ? selectable watchdog timer interval (25ms, 200ms, 1.4s or off) ? debounced manual reset input ? low power cmos ?25a typical standby current, watchdog on ?6a typical standby current, watchdog off ? memory security ? 4kbits of eeprom ?16 byte page write mode ?5ms write cycle time (typical) ? built-in inadvertent write protection ?power-up/power-down protection circuitry ?block lock protect 0, or 1/2, of eeprom ? 400khz 2-wire interface ? 2.7v to 5.5v power supply operation ? available packages ?14 ld soic, tssop ? pb-free plus anneal available (rohs compliant) applications ? communication equipment ?routers, hubs, switches ?disk arrays, network storage ? industrial systems ?process control ?intelligent in strumentation ? computer systems ?computers ?network servers description the x40430, x40431, x40434, x40435 combines power-on reset control, watchdog timer, supply voltage supervision, second and third voltage supervision, manual reset, and block lock ? protect serial eeprom in one package. this combin ation lowers system cost, reduces board space requirements, and increases reliability. applying voltage to v cc activates the power-on reset circuit which hol ds reset/reset active for a period of time. this allows the power supply and system oscilla- tor to stabilize before the pr ocessor can execute code. low v cc detection circuitry protects the user?s system from low voltage condit ions, resetting the system when v cc falls below the minimum v trip1 point. reset/reset is active until v cc returns to proper operating level and stabilizes . a second and third volt- age monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. three common low voltage combinations are available. however, intersil?s unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet specific system level requirements or to fine-tune the threshold for applica- tions requiring higher precision. a manual reset input provides debounce circuitry for minimum reset component count. the watchdog timer provides an independent protec- tion mechanism for microcontrollers. when the micro- controller fails to restart a timer within a selectable time out interval, the device activates the wdo signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the memory portion of the device is a cmos serial eeprom array with in tersil?s block lo ck protection. the array is internally organized as x 8. the device features a 2-wire interface and software protocol allowing operation on an i 2 c bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. data sheet may 24, 2006
2 fn8251.1 may 24, 2006 block diagram *voltage monitor requires vcc to operate. others are independent of vcc. v3fail v2fail wdo mr lowline reset reset x40430/34 x40431/35 v3 monitor logic v2 monitor logic fault detection register status register eeprom array data register command decode test & control logic power-on, manual reset low voltage reset generation v cc monitor logic v3mon v2mon sda wp scl v cc (v1mon) + - + - watchdog and reset logic v trip3 + - v trip2 v trip1 *x40430, x40431= v cc or v2mon* v2mon x40434, x40435 = v cc device expected system voltages vtrip1(v) v trip2(v) vtrip3(v) por (system) x40430, x40431 -a -b -c 5v; 3v or 3.3v; 1.8v 5v; 3v; 1.8v 3.3v; 2.5v; 1.8v 2.0?4.75* 4.55?4.65* 4.35?4.45* 2.95?3.05* 1.70?4.75 2.85?2.95 2.55?2.65 2.15?2.25 1.70?4.75 1.65?1.75 1.65?1.75 1.65?1.75 reset = x40430 reset = x40431 x40434, x40435 -a -b -c 5v; 3.3v; 1.5v 5v; 3v or 3.3v; 1.5v 5v; 3 or 3.3v; 1.2v 2.0?4.75* 4.55?4.65* 4.55?4.65* 4.55?4.65* 0.90?3.50* 1.25?1.35* 1.25?1.35* 0.95?1.05* 1.70?4.75 3.05?3.15 2.85?2.95 2.85?2.95 reset = x40434 reset = x40435 x40430, x40431, x40434, x40435
3 fn8251.1 may 24, 2006 ordering information part number* part marking monitored v cc range v trip1 range v trip2 range v trip3 range temp. range (c) package pkg. dwg. # part number with reset x40430s14-c x40430s c 1.7 to 3.6 2.9v 50mv 2.2v 50mv 1.7v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40430s14i-c x40430s ic -40 to +85 14 ld soic (150 mil) m14.15 x40430v14-c x4043 0vc 0 to 70 14 ld tssop (4.4mm) m14.173 x40430v14i-c x4043 0vic -40 to +85 14 ld tssop (4.4mm) m14.173 x40430s14-b x40430s b 1.7 to 5.5 4.4v 50mv 2.6v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40430s14z-b (note) x40430s zb 0 to 70 14 ld soic (150 mil) (pb-free) m14.15 x40430s14i-b x40430s ib -40 to +85 14 ld soic (150 mil) m14.15 x40430s14iz-b (note) x40430s zib -40 to +85 14 ld soic (150 mil) (pb-free) m14.15 x40430v14-b x4043 0vb 0 to 70 14 ld tssop (4.4mm) m14.173 x40430v14z-b (note) x40430v zb 0 to 70 14 ld tssop (4.4mm) (pb-free) m14.173 x40430v14i-b x4043 0vib -40 to +85 14 ld tssop (4.4mm) m14.173 x40430v14iz-b (note) x40430v zib -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x40434s14-c x40434s c 1.0 to 5.5 4.6v 50mv 1.0v 50mv 2.9v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40434s14i-c x40434s ic -40 to +85 14 ld soic (150 mil) m14.15 x40434v14-c x40434v c 0 to 70 14 ld tssop (4.4mm) m14.173 x40434v14i-c x40434v ic -40 to +85 14 ld tssop (4.4mm) m14.173 x40434s14-b x40434s b 1.3 to 5.5 1.3v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40434s14z-b (note) x40434s zb 1.3 to 5.5 0 to 70 14 ld soic (150 mil) (pb-free) m14.15 x40434s14i-b x40434s ib 1.3 to 5.5 -40 to +85 14 ld soic (150 mil) m14.15 x40434s14iz-b (note) x40434s zib 1.3 to 5.5 -40 to +85 14 ld soic (150 mil) (pb-free) m14.15 x40434v14-b x40434v b 1.3 to 5.5 0 to 70 14 ld tssop (4.4mm) m14.173 x40434v14z-b (note) x40434v zb 1.3 to 5.5 0 to 70 14 ld tssop (4.4mm) (pb-free) m14.173 x40434v14i-b x40434v ib 1.3 to 5.5 -40 to +85 14 ld tssop (4.4mm) m14.173 x40434v14iz-b (note) x4043 4v zib 1.3 to 5.5 -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x40434s14-a x40434s a 1.3 to 5.5 3.1v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40434s14z-a (note) x40434s za 1.3 to 5.5 0 to 70 14 ld soic (150 mil) (pb-free) m14.15 x40434s14i-a x40434s ia 1.3 to 5.5 -40 to +85 14 ld soic (150 mil) m14.15 x40434s14iz-a (note) x40434s zia 1.3 to 5.5 -40 to +85 14 ld soic (150 mil) (pb-free) m14.15 x40430, x40431, x40434, x40435
4 fn8251.1 may 24, 2006 x40434v14-a x40434v a 1.3 to 5.5 4.6v 50mv 1.3v 50mv 3.1v 50mv 0 to 70 14 ld tssop (4.4mm) m14.173 x40434v14z-a (note) x40434v za 0 to 70 14 ld tssop (4.4mm) (pb-free) m14.173 x40434v14i-a x40434v ia -40 to +85 14 ld tssop (4.4mm) m14.173 x40434v14iz-a (note) x40434vzia -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x40430s14-a x40430s a 1.7 to 5.5 2.9v 50mv 1.7v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40430s14z-a (note) x40430s za 0 to 70 14 ld soic (150 mil) (pb-free) m14.15 x40430s14i-a x40430s ia -40 to +85 14 ld soic (150 mil) m14.15 x40430s14iz-a (note) x40430s zia -40 to +85 14 ld soic (150 mil) (pb-free) m14.15 x40430v14-a x4043 0va 0 to 70 14 ld tssop (4.4mm) m14.173 x40430v14z-a (note) x40430v za 0 to 70 14 ld tssop (4.4mm) (pb-free) m14.173 x40430v14i-a x4043 0via -40 to +85 14 ld tssop (4.4mm) m14.173 x40430v14iz-at1 (note) x4043 0vzia -40 to +85 14 ld tssop tape and reel (4.4mm) (pb-free) m14.173 part number with reset x40431s14-c x40431s c 1.7 to 3.6 2.9v 50mv 2.2v 50mv 1.7v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40431s14i-c x40431s ic -40 to +85 14 ld soic (150 mil) m14.15 x40431v14-c x40431v c 0 to 70 14 ld tssop (4.4mm) m14.173 x40431v14i-c x40431 ic -40 to +85 14 ld tssop (4.4mm) m14.173 x40431s14-b x40431s b 1.7 to 5.5 4.4v 50mv 2.6v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40431s14z-b (note) x40431s zb 0 to 70 14 ld soic (150 mil) (pb-free) m14.15 x40431s14i-b x40431s ib -40 to +85 14 ld soic (150 mil) m14.15 x40431s14iz-b (note) x40431s zib -40 to +85 14 ld soic (150 mil) (pb-free) m14.15 x40431v14-b x40431v b 0 to 70 14 ld tssop (4.4mm) m14.173 x40431v14z-b (note) x40431v zb 0 to 70 14 ld tssop (4.4mm) (pb-free) m14.173 x40431v14i-b x40431v ib -40 to +85 14 ld tssop (4.4mm) m14.173 x40431v14iz-b (note) x40431v zib -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x40435s14-c x40435 c 1.0 to 5.5 4.6v 50mv 1.0v 50mv 2.9v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40435s14i-c x40435 ic -40 to +85 14 ld soic (150 mil) m14.15 x40435v14-c x40435 c 0 to 70 14 ld tssop (4.4mm) m14.173 x40435v14i-c x40435 ic -40 to +85 14 ld tssop (4.4mm) m14.173 ordering information (continued) part number* part marking monitored v cc range v trip1 range v trip2 range v trip3 range temp. range (c) package pkg. dwg. # x40430, x40431, x40434, x40435
5 fn8251.1 may 24, 2006 x40435s14-b x40435 b 1.3 to 5.5 4.6v 50mv 1.3v 50mv 2.9v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40435s14z-b (note) x40435s zb 0 to 70 14 ld soic (150 mil) (pb-free) m14.15 x40435s14i-b x40435 ib -40 to +85 14 ld soic (150 mil) m14.15 x40435s14iz-b (note) x40435s zib -40 to +85 14 ld soic (150 mil) (pb-free) m14.15 x40435v14-b x40435 b 0 to 70 14 ld tssop (4.4mm) m14.173 x40435v14z-b (note) x40435v zb 0 to 70 14 ld tssop (4.4mm) (pb-free) m14.173 x40435v14i-b x40435 ib -40 to +85 14 ld tssop (4.4mm) m14.173 x40435v14iz-b (note) x40435v zib -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x40435s14-a x40435 a 3.1v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40435s14z-a (note) x40435s za 0 to 70 14 ld soic (150 mil) (pb-free) m14.15 x40435s14i-a x40435 ia -40 to +85 14 ld soic (150 mil) m14.15 x40435s14iz-a (note) x40435s zia -40 to +85 14 ld soic (150 mil) (pb-free) m14.15 x40435v14-a x40435 a 0 to 70 14 ld tssop (4.4mm) m14.173 x40435v14z-a (note) x40435v za 0 to 70 14 ld tssop (4.4mm) (pb-free) m14.173 x40435v14i-a x40435 ia -40 to +85 14 ld tssop (4.4mm) m14.173 x40435v14iz-a (note) x40435v zia -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x40431s14-a x40431s a 1.7 to 5.5 2.9v 50mv 1.7v 50mv 0 to 70 14 ld soic (150 mil) m14.15 x40431s14z-a (note) x40431s za 0 to 70 14 ld soic (150 mil) (pb-free) m14.15 x40431s14i-a x40431s ia -40 to +85 14 ld soic (150 mil) m14.15 x40431s14iz-a (note) x40431s zia -40 to +85 14 ld soic (150 mil) (pb-free) m14.15 x40431v14-a x40431v a 0 to 70 14 ld tssop (4.4mm) m14.173 x40431v14z-a (note) x40431v za 0 to 70 14 ld tssop (4.4mm) (pb-free) m14.173 x40431v14i-a x40431v ia -40 to +85 14 ld tssop (4.4mm) m14.173 x40431v14iz-a (note) x40431v zia -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number* part marking monitored v cc range v trip1 range v trip2 range v trip3 range temp. range (c) package pkg. dwg. # x40430, x40431, x40434, x40435
6 fn8251.1 may 24, 2006 pin configuration v3mon v ss v cc sda scl 3 2 4 1 12 13 11 14 lowline nc reset 7 6 5 8 9 10 v2mon mr wp 3 2 4 1 12 13 11 14 7 6 5 8 9 10 v3fail wdo v2fail v3mon v cc sda scl wp v3fail wdo v ss lowline nc reset v2mon mr v2fail x40430, x40434 x40431, x40435 14 ld soic, tssop 14 ld soic, tssop pin description pin name function 1v2fail v2 voltage fail output. this open drain output goes low when v2mon is less than v trip2 and goes high when v2mon exceeds v trip2 . there is no power-up reset delay circuitry on this pin. 2v2mon v2 voltage monitor input. when the v2mon input is less than the v trip2 voltage, v2fail goes low. this input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. connect v2mon to v ss or v cc when not used. the v2mon comparator is supplied by v2mon (x40430, x40431) or by the v cc input (x40434, x40435). 3lowline early low v cc detect. this cmos output signal goes low when v cc < v trip1 and goes high when v cc > v trip1 . 4nc no connect. 5mr manual reset input. pulling the mr pin low initiates a system reset. the reset/reset pin will re- main high/low until the pin is released and for the t purst thereafter. 6 reset / reset reset output. (x40431, x40435) this open drain pin is an active low output which goes low when- ever v cc falls below v trip1 voltage or if manual reset is asserted. this output stays active for the pro- grammed time period (t purst ) on power-up. it will also stay active until manual reset is released and for t purst thereafter. reset output. (x40430, x40434) this pin is an active high cmos output which goes high when- ever v cc falls below v trip1 voltage or if manual reset is asserted. this output stays active for the pro- grammed time period (t purst ) on power-up. it will also stay active until manual reset is released and for t purst thereafter. 7v ss ground 8sda serial data. sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drai n or open collector outputs. this pin requires a pull up resistor and the input buffer is always active (not gated). watchdog input. a high to low transition on the sda (while scl is toggled from high to low and followed by a stop condition) restarts the watchdog timer. the absence of this transition within the watchdog time out period results in wdo going active. 9scl serial clock. the serial clock controls the serial bus timing for data input and output. 10 wp write protect. wp high prevents writes to any location in the device (including all the registers). it has an internal pull down resistor (>10m ? typical). 11 v3mon v3 voltage monitor input. when the v3mon input is less than the v trip3 voltage, v3fail goes low. this input can monitor an unregulated power supply with an external resistor divider or can monitor a third power supply with no external components. connect v3mon to v ss or v cc when not used. the v3mon comparator is supplied by the v3mon input. 12 v3fail v3 voltage fail output. this open drain output goes low when v3mon is less than v trip3 and goes high when v3mon exceeds v trip3 . there is no power-up reset delay circuitry on this pin. 13 wdo wdo output. wdo is an active low, open drain output which goes active whenever the watchdog timer goes active. 14 v cc supply voltage x40430, x40431, x40434, x40435
7 fn8251.1 may 24, 2006 principles of operation power-on reset applying power to the x40430, x40431, x40434, x40435 activates a power- on reset circuit that pulls the reset/reset pins active. this signal provides several benefits. ? it prevents the system micr oprocessor from starting to operate with insufficient voltage. ? it prevents the processor from operating prior to sta- bilization of the oscillator. ? it allows time for an fpga to download its configura- tion prior to initialization of the circuit. ? it prevents communication to the eeprom, greatly reducing the likelihood of data corruption on power-up. when v cc exceeds the device v trip1 threshold value for t purst (selectable) the circ uit releases the reset (x40431, x40435) and reset (x40430, x40434) pin allowing the system to begin operation. figure 1. connecting a manual reset push-button manual reset by connecting a push-button directly from mr to ground, the designer adds manual syst em reset capability. the mr pin is low while the push-button is closed and reset/reset pin remains high/l ow until the push- button is released and for t purst thereafter. low voltage v cc (v1 monitoring) during operation, the x40430, x40431, x40434, x40435 monitors the v cc level and asserts reset/reset if supply voltage falls below a preset minimum v trip1 . the reset/reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset/reset signal remains active until the vo ltage drops below 1v. it also remains active until v cc returns and exceeds v trip1 for t purst . low voltage v2 monitoring the x40430 also monitors a second voltage level and asserts v2fail if the voltage falls below a preset mini- mum v trip2 . the v2fail signal is either ored with reset to prevent the micr oprocessor from operating in a power fail or brownout condition or used to inter- rupt the microprocessor with notification of an impend- ing power failure. for the x40430 and x40431 the v2fail signal remains active until the v2mon drops below 1v (v2mon falling). it also remain s active until v2mon returns and exceeds v trip2 . this voltage sense cir- cuitry monitors the power supply connected to v2mon pin. if v cc = 0, v2mon can still be monitored. for the x40434 and x40435, the v2fail signal remains active until v cc drops below 1v and remains active until v2mon returns and exceeds v trip2 . this sense circuitry is powered by v cc . if v cc = 0, v2mon cannot be monitored. low voltage v3 monitoring the x40430, x40431, x40434, x40435 also monitors a third voltage level and asserts v3fail if the voltage falls below a preset minimum v trip3 . the v3fail sig- nal is either ored with r eset to prevent the micro- processor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. the v3fail signal remains active until the v3mon drops below 1v (v3mon falling). it also re mains active until v3mon returns and exceeds v trip3 . this voltage sense circuitry monitors the power supply connected to v3mon pin. if v cc = 0, v3mon can still be monitored. early low v cc detection (lowline ) this cmos output goes low earlier than reset/reset whenever v cc falls below the v trip1 voltage and returns high when v cc exceeds the v trip1 voltage. there is no power-up delay circuitry (t purst ) on this pin. v cc mr system reset manual reset x40430, x40434 reset x40430, x40431, x40434, x40435
8 fn8251.1 may 24, 2006 figure 2. two uses of multiple voltage monitoring figure 3. v tripx set/reset conditions watchdog timer the watchdog timer circuit monitors the microproces- sor activity by monitoring the sda and scl pins. a standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the wdo signal going active. a minimum sequence to reset the watchdog timer requires four microprocessor instructions namely, a start, clock low, clock high and stop. the state of two nonvolatile control bits in the status register dete rmine the watchdog timer period. the microprocessor can change these watch- dog bits by writing to the x40430, x40431, x40434, x40435 control register (also refer to page 20). figure 4. watchdog restart v1, v2 and v3 th reshold program procedure (optional) the x40430 is shipped with standard v1, v2 and v3 threshold (v trip1, v trip2, v trip3 ) voltages. these values will not change over normal operating and stor- age conditions. however, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the x40430, x40431, x40434, x40435 trip points may be adjusted. the procedure is described in the following situation, and uses the application of a high voltage control sig- nal. 6-10v v cc 5v v3mon x40431-a unreg. supply v cc x40431-b reset v2fail system v cc reset v2fail v3fail system reset notice: no external components required to monitor three voltages. 1m v3mon v3fail v2mon 5v reg 3.0v reg 1.8v reg 3.3v 390k v2mon reset power fail interrupt v cc (1.7v) v cc /v2mon/v3mon v tripx v p t wc a0h 0 7 70 7 0 scl wdo sda (x = 1, 2, 3) 00h scl sda .6s 1.3s wdt reset start stop x40430, x40431, x40434, x40435
9 fn8251.1 may 24, 2006 setting a v tripx voltage (x = 1, 2, 3) there are two procedures used to set the threshold voltages (v tripx ), depending if the threshold voltage to be stored is higher or lower than the present value. for example, if the present v tripx is 2.9 v and the new v tripx is 3.2 v, the new voltage can be stored directly into the v tripx cell. if however, the new setting is to be lower than the presen t setting, then it is neces- sary to ?reset? the v tripx voltage before setting the new value. setting a higher v tripx voltage (x = 1, 2, 3) to set a v tripx threshold to a new voltage which is higher than the present threshold, the user must apply the desired v tripx threshold voltage to the corre- sponding input pin vcc(v1mon), v2mon or v3mon. then, a programming voltage (vp) must be applied to the wdo pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h, fol- lowed by the byte address 01h for v trip1 , 09h for v trip2 , and 0dh for v trip3 , and a 00h data byte in order to program v tripx . the stop bit following a valid write operation initiates the programming sequence. pin wdo must then be brought low to complete the operation. to check if the v tripx has been set, set vxmon to a value slightly greater than v tripx (that was previously set). slowly ramp down vxmon and observe when the corre- sponding outputs (lowline , v2fail and v3fail ) switch. the voltage at which this occurs is the v tripx (actual). c ase a now if the desired v tripx is greater than the v tripx (actual), then add the difference between v tripx (desired) ? v tripx (actual) to the original v tripx desired. this is your new v tripx that should be applied to vxmon and the whole sequence should be repeated again (see figure 5). c ase b now if the v tripx (actual), is higher than the v tripx (desired), perform the reset sequence as described in the next section. the new v tripx voltage to be applied to vxmon will now be: v tripx (desired) ? (v tripx (actual) ? v tripx (desired)). note: this operation does not corrupt the memory array. setting a lower v tripx voltage (x = 1, 2, 3) in order to set v tripx to a lower voltage than the present value, then v tripx must first be ?reset? accord- ing to the procedure described below. once v tripx has been ?reset?, then v tripx can be set to the desired voltage using the procedure described in ?setting a higher v tripx voltage?. resetting the v tripx voltage to reset a v tripx voltage, apply the programming volt- age (vp) to the wdo pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h followed by the byte address 03h for v trip1 , 0bh for v trip2 , and 0fh for v trip3 , followed by 00h for the data byte in order to reset v tripx . the stop bit following a valid wr ite operation initiates the programming sequence. pin wdo must then be brought low to complete the operation. after being reset, the value of v tripx becomes a nomi- nal value of 1.7v or lesser. notes: 1. this operation does not corrupt the memory array. 2. set v cc ? 1.5(v2mon or v3mon), when setting v trip2 or v trip3 respectively. control register the control register prov ides the user a mechanism for changing the block lock and watchdog timer set- tings. the block lock and watchdog timer bits are nonvolatile and do not change when power is removed. the control register is ac cessed with a special pream- ble in the slave byte (1011) and is located at address 1ffh. it can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write opera- tion. prior to writing to the control register, the wel and rwel bits must be set using a two step process, with the whole sequence requi ring 3 steps. see "writing to the control registers" on page 11. the user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores wd1, wd0, pup1, pup0, and bp. the x40430, x40431, x40434, x40435 will not acknowledge any data bytes written after th e first byte is entered. the state of the control register can be read at any time by performing a random read at address 1ffh, using the special preamble. only one byte is read by each register read operat ion. the master should supply a stop condition to be consistent with the bus protocol. rwel: register write en able latch (volatile) the rwel bit must be set to ?1? prior to a write to the control register. 76543 210 pup1 wd1 wd0 bp 0 rwel wel pup0 x40430, x40431, x40434, x40435
10 fn8251.1 may 24, 2006 figure 5. sample v trip reset circuit figure 6. v tripx set/reset sequence (x = 1, 2, 3) wel: write enable latch (volatile) the wel bit controls the access to the memory and to the register during a write operation. this bit is a vola- tile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address, including any control regi sters will be ignored (no acknowledge will be issued af ter the data byte). the wel bit is set by writing a ?1? to the wel bit and zeroes to the other bits of the control register. 1 6 2 7 14 13 9 8 x4043x v trip1 adj. v p sda scl c adjust run v2fail v trip2 adj. reset v tripx programming apply v cc and voltage decrease v x actual v tripx - desired v tripx done set higher v x sequence error < mde ? | error | < | mde | yes no error > mde + > desired v tripx to v x desired present value v tripx < execute no yes execute v tripx reset sequence set v x = desired v tripx new v x applied = old v x applied + | error | new v x applied = old v x applied - | error | execute reset v tripx sequence output switches? note: x = 1, 2, 3 let: mde = maximum desired error vx = v cc , vxmon mde + desired value mde ? acceptable error range error = actual - desired x40430, x40431, x40434, x40435
11 fn8251.1 may 24, 2006 once set, wel remains set until either it is reset to 0 (by writing a ?0? to the wel bit and zeroes to the other bits of the control register) or until the part powers up again. writes to the wel bit do not cause a high volt- age write cycle, so the device is ready for the next operation immediately after the stop condition. bp: block protect bits (nonvolatile) the block protect bit bp, determines which blocks of the array are write protected. a write to a protected block of memory is ignored. the block protect bit will prevent write operations to half or none of the array. pup1, pup0: power-up bits (nonvolatile) the power-up bits, pup1 and pup0, determine the t purst time delay. the nominal power-up times are shown in the following table. wd1, wd0: watchdog timer bits (nonvolatile) the bits wd1 and wd0 control the period of the watchdog timer. the options are shown below. writing to the co ntrol registers changing any of the nonvolatile bits of the control and trickle registers requir es the following steps: ? write a 02h to the control register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation pre- ceded by a start and ended with a stop). ? write a 06h to the control register to set the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation proceeded by a start and ended with a stop). ? write one byte value to the control register that has all the control bits set to the desired state. the control register can be represented as qxys 001 r in binary, where xy are the wd bits, s is the bp bit and qr are the power-up bits. this operation proceeded by a start and ended with a stop bit. since this is a nonvolatile write cycle it will take up to 10ms (max.) to complete. the rwel bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. if bit 2 is set to ?1? in this third step ( qxys 011 r ) then the rwel bit is set, but the wd1, wd0, pup1, pup0, and bp bits remain unchanged. writing a second byte to the control register is not allowed. doing so aborts the write operation and returns a nack. ? a read operation occurring between any of the previ- ous operations will not inte rrupt the regi ster write operation. ? the rwel bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. to illustrate, a sequ ence of writes to the device con- sisting of [02h, 06h, 02h] will reset all of the nonvola- tile bits in the control register to 0. a sequence of [02h, 06h, 06h] will leave the nonvolatile bits unchanged and the rwel bit remains set. notes: 1. t purst is set to 200ms as factory default. 2. watch dog timer bits are shipped disabled. fault detection register the fault detection register (fdr) provides the user the status of what causes the system reset active. the manual reset fail, watchdog timer fail and three low voltage fail bits are volatile the fdr is accessed with a special preamble in the slave byte (1011) and is located at address 0ffh. it can only be modified by performing a byte write opera- tion directly to the addres s of the register and only one data byte is allowed for each register write operation. there is no need to set the wel or rwel in the control register to access this fdr. bp protected addresses (size) memory array lock 0 none none 1 100h ? 1ffh (256 bytes) upper half of memory array pup1 pup0 power-on reset delay ( t purst ) 0 0 50ms 0 1 200ms (factory setting) 1 0 400ms 1 1 800ms wd1 wd0 watchdog time out period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory setting) 7 6543210 lv1f lv2f lv3f wdf mrf 0 0 0 x40430, x40431, x40434, x40435
12 fn8251.1 may 24, 2006 figure 7. valid data changes on the sda bus at power-up, the fdr is def aulted to all ?0?. the sys- tem needs to initialize this re gister to all ?1? before the actual monitoring can take place. in the event that any one of the monitored sour ces fail, the corresponding bit in the register will change from a ?1? to a ?0? to indi- cate the failure. at this moment, the system should perform a read to the register and note the cause of the reset. after reading the register the system should reset the register back to all ?1? again. the state of the fdr can be read at any time by performing a random read at address 0ffh, using the special preamble. the fdr can be read by performing a random read at 0ffh address of the register at any time. only one byte of data is read by the register read operation. mrf, manual reset fail bit (volatile) the mrf bit will be set to ?0? when manual reset input goes active. wdf, watchdog timer fail bit (volatile) the wdf bit will be set to ?0? when the wdo goes active. lv1f, low v cc reset fail bit (volatile) the lv1f bit will be set to ?0? when v cc (v1mon) falls below v trip1 . lv2f, low v2mon reset fail bit (volatile) the lv2f bit will be set to ?0? when v2mon falls below v trip2 . lv3f, low v3mon reset fail bit (volatile) the lv3f bit will be set to ?0? when the v3mon falls below v trip3 . serial interface interface conventions the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this fam- ily operate as slaves in all applications. serial clock and data data states on the sda line can change only during scl low. sda state cha nges during scl high are reserved for indicating start and stop conditions. see figure 7. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the st art condition and will not respond to any command until this condition has been met. see figure 8. serial stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condi tion is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has rel eased the bus. see figure 8. figure 8. valid start and stop conditions scl sda data stable data change data stable scl sda start stop x40430, x40431, x40434, x40435
13 fn8251.1 may 24, 2006 serial acknowledge acknowledge is a software convention used to indi- cate successful data transf er. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during t he ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. see figure 9. the device will respond wit h an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data . the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. serial write operations byte write for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of th e word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the de vice will not respond to any requests from the master. the sda output is at high impedance. see figure 10. a write to a protected block of memory will suppress the acknowledge bit. figure 9. acknowledge response from receiver figure 10. byte write sequence data output from transmitter data output from receiver 8 1 9 start acknowledge scl from master s t a r t s t o p slave address byte address data a c k a c k a c k sda bus signals from the slave signals from the master 0 x40430, x40431, x40434, x40435
14 fn8251.1 may 24, 2006 page write the device is capable of a page write operation. it is initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transfer red, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the device will respond with an acknowl- edge, and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to ?0? on the same page. this means that the master can write 16 bytes to the page starting at any location on that page. if the mas- ter begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. afterwards, the address counter would point to location 6 of the page that was just written. if the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. the master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. as wi th the byte write operation, all inputs are disabled until completion of the internal write cycle. see figure 11 for the address, acknowl- edge, and data transfer sequence. stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself without performing t he write. the contents of the array will not be effected. acknowledge polling the disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indi- cate the end of the master?s byte load operation, the device initiates the inte rnal high voltage cycle. acknowledge polling can be initiated immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the high voltage cycle then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. see figure 13. serial read operations read operations are initiated in the same manner as write operations with th e exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, ran- dom reads, and sequential reads. figure 11. page write operation figure 12. writing 12 bytes to a 16-byte page starting at location 10. s t a r t s t o p slave address byte address data (n) a c k a c k a c k sda bus signals from the slave signals from the master 0 data (1) a c k (1 n 16) 1010 0 0 address address 10 5 bytes n-1 7 bytes address = 6 address pointer ends here addr = 7 x40430, x40431, x40434, x40435
15 fn8251.1 may 24, 2006 current address read internally the device contains an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. on power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. see figure 15 for the address, acknowledge, and data transfer sequence. figure 13. acknowledge polling sequence it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. random read random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipts of the word address bytes, the master immediately issues another start con- dition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. see figure 16 for the address, acknowledge, and data transfer sequence. a similar operation called ?set current address? where the device will perfor m this operation if a stop is issued instead of the second start is shown in figure 15. the device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. this operation loads the new address into the address counter. the next current address read operation will read from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. sequential read sequential reads can be initiated as either a current address read or random address read. the first data byte is transmitted as with the other modes; however, the master now responds wi th an acknowledge, indicat- ing it requires additional data. the device continues to output data for each acknowledge received. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequentia l, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one opera- tion. at the end of the addres s space the counter ?rolls over? to address 0000h and the device continues to out- put data for each acknowledge received. see figure 17 for the acknowledge and data transfer sequence. ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes x40430, x40431, x40434, x40435
16 fn8251.1 may 24, 2006 serial device addressing memory address map cr, control register, cr7: cr0 address: 1ff hex fdr, fault detectionregister, fdr7: fdr0 address: 0ff hex general purpose memory organization, a8:a0 address: 000h to 1ffh general purpose memory array configuration slave address byte following a start condition, the master must output a slave address byte. this byte consists of several parts: ? a device type identifier that is always ?101x?. where x = 0 is for array, x = 1 is for control register or fault detection register. ? next two bits are ?0?. ? next bit that becomes the msb of the address. figure 14. x40430, x40431, x40434, x40435 addressing ? last bit of the slave command byte is a r/w bit. the r/w bit of the slave address byte defines the oper- ation to be performed. when the r/w bit is a one, then a read operation is selected. a zero selects a write operation. word address the word address is either supplied by the master or obtained from an internal counter. the internal counter is undefined on a power-up condition. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? the wel bit is set to ?0?. in this state it is not possi- ble to write to the device. ? sda pin is the input mode. ? reset/reset signal is active for t purst . data protection the following circuitry has been included to prevent inadverten t writes: ? the wel bit must be set to allow write operations. ? the proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. ? a three step sequence is required before writing into the control register to change watchdog timer or block lock settings. ? the wp pin, when held hi gh, prevents all writes to the array and all the register. figure 15. current address read sequence . memory address a8:a0 000h 0ffh 100h 1ffh lower 256 bytes upper 256 bytes block protect option general purpose memory control register fault detection register 1 1 0 0 1 1 0 1 a8 r/w word address slave byte 1 0 1011 0 0 0 0 0 0 r/w r/w general purpose memory control register fault detection register a7 1 a6 a5 a4 a1 a0 1 a3 a2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 s t a r t s t o p slave address data sda bus signals from the slave signals from the master 1 a c k 1010 0 0 x40430, x40431, x40434, x40435
17 fn8251.1 may 24, 2006 figure 16. random address read sequence figure 17. sequential read sequence 0 slave address byte address a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master 101 0 0 data (2) s t o p slave address data (n) a c k a c k sda bus signals from the slave signals from the master 1 data (n-1) a c k a c k (n is any integer greater than 1) data (1) x40430, x40431, x40434, x40435
18 fn8251.1 may 24, 2006 absolute maximum ratings temperature under bias .................... -65c to +135c storage temperature ......................... -65c to +150c voltage on any pin with respect to v ss ...................................... -1.0v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10s) .................... 300c comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating con- ditions for extended periods ma y affect device reliability. recommended operating conditions *see ordering info temperature min. max. commercial 0c 70c industrial -40c +85c version chip supply voltage monitored* voltages x40430, x40431 2.7v to 5.5v 1.7v to 5.5v x40434, x40435 2.7v to 5.5v 1.0v to 5.5v d.c. operating characteristics (over the recommended operating cond itions unless otherwise specified) symbol parameter min typ (4) max unit test conditions i cc1 (1) active supply current ( v cc ) read 1.5 ma v il = v cc x 0.1 v ih = v cc x 0.9, f scl = 400khz i cc2 (1) active supply current ( v cc ) write 3.0 ma i sb1 (1)(6) standby current ( v cc ) ac (wdt off) 6 10 a v il = v cc x 0.1 vih = v cc x 0.9 f scl , f sda = 400khz i sb2 (2)(6) standby current ( v cc ) dc (wdt on) 25 30 a v sda = v scl = v cc others = gnd or v cc i li input leakage current (scl, mr , wp) 10 a v il = gnd to v cc i lo output leakage current (sda, v2fail , v3fail , wdo , reset ) 10 a v sda = gnd to v cc device is in standby (2) v il (3) input low voltage (sda, scl, mr , wp) -0.5 v cc x 0.3 v v ih (3) input high voltage (sda, scl, mr , wp) v cc x 0.7 v cc + 0.5 v v hys (6) schmitt trigger input hysteresis ? fixed input level ? v cc related level 0.2 .05 x v cc v v v ol output low voltage (sda, re- set/reset , lowline , v2fail , v3fail , wdo ) 0.4 v i ol = 3.0ma (2.7-5.5v) i ol = 1.8ma (2.7-3.6v) v oh output (reset, lowline ) high voltage v cc ? 0.8 v cc ? 0.4 vi oh = -1.0ma (2.7-5.5v) i oh = -0.4ma (2.7-3.6v) x40430, x40431, x40434, x40435
19 fn8251.1 may 24, 2006 notes: (1) the device enters the active state after any start, and re mains active until: 9 clock cycl es later if the device selec t bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into st andby: 200ns after any stop, except those th at initiate a high voltage write cycle; t wc after a stop that initiates a high voltage cycle; or 9 clock cycles after any st art that is not followed by the correct de vice select bits in the slave address by te. (3) v il min. and v ih max. are for reference only and are not tested. (4) at 25c, v cc = 3v (5) see ordering information for standard programming leve ls. for custom programmed levels, contact factory. (6) based on characterization data. equivalent input circuit for vxmon (x = 1, 2, 3) capacitance v cc supply v trip1 (5) v cc trip point voltage range 2.0 4.75 v 4.55 4.6 4.65 v x40430, x40431-a, x40434, x40435 4.35 4.4 4.45 v x40430, x40431-b 2.85 2.9 2.95 v x40430, x40431-c second supply monitor i v2 v2mon current 15 a v trip2 (5) v2mon trip point voltage range 1.7 0.9 4.75 3.5 v v x40430, x40431 x40434, x40435 2.85 2.9 2.95 v x40430, x40431-a 2.55 2.6 2.65 v x40430, x40431-b 2.15 2.2 2.25 v x40430, x40431-c 1.25 1.3 1.35 v x40434, x40435-a&b 0.95 1.0 1.05 v x40434, x40435-c t rpd2 (6) v trip2 to v2fail 5s third supply monitor i v3 v3mon current 15 a v trip3 (5) v3mon trip point voltage range 1.7 4.75 v 1.65 1.7 1.75 v x40430, x40431 3.05 3.1 3.15 v x40434, x40435-a 2.85 2.9 2.95 v x40434, x40435-b&c t rpd3 (6) v trip3 to v3fail 5s d.c. operating characteristics (continued) (over the recommended operating cond itions unless otherwise specified) symbol parameter min typ (4) max unit test conditions + ? v ref t rpdx = 5s worst case output pin vxmon r c ? v = 100mv ? v v ref symbol parameter max unit test conditions c out (1) output capacitance (sda, reset/reset , lowline , v2fail ,v3fail , wdo ) 8pf v out = 0v c in (1) input capacitance (scl, wp, mr ) 6 pf v in = 0v note: (1) this parameter is not 100% tested. x40430, x40431, x40434, x40435
20 fn8251.1 may 24, 2006 equivalent a.c. output load circuit for v cc = 5v a.c. test conditions symbol table a.c. characteristics note: (1) cb = total capacitance of one bus line in pf. input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load 5v sda 30pf v2mon, v3mon 4.6k ? reset 30pf 2.06k ? v2fail , v cc 4.6k ? 30pf wdo v3fail must be steady will be steady may change from low will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance waveform inp uts outputs to high symbol parameter min max unit f scl scl clock frequency 400 khz t in pulse width suppression time at inputs 50 ns t aa scl low to sda data out valid 0.1 0.9 s t buf time the bus free before start of new transmission 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh data output hold time 50 ns t r sda and scl rise time 20 +.1cb (1) 300 ns t f sda and scl fall time 20 +.1cb (1) 300 ns t su:wp wp setup time 0.6 s t hd:wp wp hold time 0 s cb capacitive load for each bus line 400 pf x40430, x40431, x40434, x40435
21 fn8251.1 may 24, 2006 timing diagrams bus timing wp pin timing write cycle timing nonvolatile write cycle timing note: (1) t wc is the time from a valid stop condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless ac knowledge polling is used. t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t r t dh t aa t hd:wp scl sda in wp t su:wp clk 1 clk 9 slave address byte start scl sda t wc 8 th bit of last byte ack stop condition start condition symbol parameter min typ max unit t wc (1) write cycle time 5 10 ms x40430, x40431, x40434, x40435
22 fn8251.1 may 24, 2006 power fail timings reset/reset /mr timings v2mon or v2fail or t r t f t rpdx v rvalid v3mon v3fail lowline or v cc v tripx t rpdx t rpdx t rpdl t rpdl t rpdl x = 2, 3 [] [] low voltage and watchdog timings parameters (@25c, v cc = 5v) symbol parameters min typ (1) max unit t rpd1 (2) t rpdl v trip1 to reset /reset (power-down only) v trip1 to lowline 5s t lr lowline to reset/reset delay (power-down only) [= t rpd1 -t rpdl ] 500 ns t rpdx (2) v trip2 to v2fail , or v trip3 to v3fail (x = 2, 3) 5 s t purst power-on reset delay: pup1 = 0, pup0 = 0 pup1 = 0, pup0 = 1 (factory setting) pup1 = 1, pup0 = 0 pup1 = 1, pup0 = 1 50 (2) 200 400 (2) 800 (2) ms ms ms ms t f v cc, v2mon , v3mon , fall time 20 mv / s t r v cc, v2mon , v3mon , rise time 20 mv / s v rvalid reset valid v cc 1v t md (2) mr to reset/ reset delay (activation only) 500 ns v cc v trip1 reset reset t purst t purst t r t f t rpd1 v rvalid mr t md t in1 x40430, x40431, x40434, x40435
23 fn8251.1 may 24, 2006 notes: (1) v cc = 5v at 25c. (2) values based on characterization data only. watchdog time out for 2-wire interface t in1 pulse width for mr 5s t wdo watchdog timer period: wd1 = 0, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 1, wd0 = 0 wd1 = 1, wd0 = 1 (factory setting) 1.4 (2) 200 (2) 25 off s ms ms t rst1 watchdog reset time out delay wd1 = 0, wd0 = 0 wd1 = 0, wd0 = 1 100 200 300 ms t rst2 watchdog reset time out delay wd1 = 1, wd0 = 0 12.5 25 37.5 ms t rsp watchdog timer restart pulse width 1 s low voltage and watchdog timings parameters (@25c, v cc = 5v) (continued) symbol parameters min typ (1) max unit < t wdo t rst wdo sda start t wdo t rst scl start t rsp wdt restart start sda scl minimum sequence to reset wdt clockin (0 or 1) x40430, x40431, x40434, x40435
24 fn8251.1 may 24, 2006 v tripx set/reset conditions v trip1 , v trip2 , v trip3 programming specifications: v cc = 2.0 - 5.5v; temperature = 25c parameter description min. max. unit t vps wdo program voltage setup time 10 s t vph wdo program voltage hold time 10 s t tsu v tripx level setup time 10 s t thd v tripx level hold (stable) time 10 s t wc v tripx program cycle 10 ms t vpo program voltage off time before next cycle 1 ms v p programming voltage 15 18 v v tran1 v trip1 set voltage range 2.0 4.75 v v tran2 v trip2 set voltage range ? x40430, x40431 1.7 4.75 v v tran2a v trip2 set to voltage range ? x40434, x40435 0.9 3.5 v v tran3 v trip3 set voltage range 1.7 4.75 v v tv v tripx set voltage variation after programming (-40 to +85c). -25 +25 mv t vps wdo program voltage setup time 10 s scl sda v cc /v2mon/v3mon (v tripx ) wdo t tsu t thd t vph t vps v p t wc t vpo a0h 0 7 70 7 *0dh sets v trip1 sets v trip2 sets v trip3 *01h *09h *03h *0bh *0fh resets v trip3 resets v trip2 resets v trip1 0 start * all others reserved 00h * x40430, x40431, x40434, x40435
25 fn8251.1 may 24, 2006 x40430, x40431, x40434, x40435 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) tolerance notes a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. l 2/01 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
26 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8251.1 may 24, 2006 x40430, x40431, x40434, x40435 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06

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